1. Field of the Invention
The present invention relates to a modulation apparatus, a modulation method adopted by the modulation apparatus, a modulation program implementing the modulation method, a recording medium for storing a signal modulated by the modulation apparatus and a recording medium for storing the modulation program. More particularly, the present invention relates to a modulation apparatus capable of executing DSV control with a high degree of reliability even if an even/odd-characteristic retention violating conversion pattern is used as well as relates to a modulation method adopted by the modulation apparatus, a modulation program implementing the modulation method, a recording medium for storing a signal modulated by the modulation apparatus and a recording medium for storing the modulation program.
2. Description of the Related Art
Before data is transmitted through a predetermined transmission line or recorded onto a recording medium such as a magnetic disk, an optical disk or a magneto-optical disk, the data is modulated to convert the data into one suitable for the transmission line or the recording medium. One of methods to modulate the data is the commonly known block coding method. In accordance with the block coding method, data is divided into data words and, then, each of the data words is converted into a code word having a size of n×i bits in accordance with a proper coding rule. The data word is a data unit having a size of m×i bits. For i=1, the resulting code is a fixed-length code. For i having a selectable variable value in the range 1 to imax, on the other hand, the resulting code is a variable-length code. The code resulting from a coding process adopting the block coding method is represented by a variable-length code (d, k; m, n; r).
The parameter i is referred to as a restrain length and the range upper limit imax is referred to as a maximum restrain length. The parameter d is the minimum number of consecutive 0s inserted between two consecutive 1s. That is to say, the parameter d is the 0 minimum run. On the other hand, the parameter k is the maximum number of consecutive 0s inserted between two consecutive 1s. That is to say, the parameter k is the 0 maximum run.
By the way, code words obtained as described above are recorded onto an optical disk or a magneto-optical disk such as a compact disk (CD) or a mini disk (MD, which is also a trademark) by carrying out a recording process in which the code words are subjected to NRZI (NonReturn to Zero Inverted) modulation processing and data is recorded onto the recording medium on the basis of a variable-length code sequence obtained as a result of the NRZI modulation processing. The NRZI modulation processing is a process to invert each 1 in the input variable-length code sequence and not inverting every 0 in the sequence. In the following description, the variable-length code sequence obtained as a result of the NRZI modulation processing is referred to as a recording waveform sequence. Such a recording process is referred to hereafter as a mark edge recording process. In the case of a magneto-optical disk or the like used as a recording medium as a disk having a size of 3.5 inches and a recording capacity of 230 MB in conformity with the ISO standards, on the other hand, the code sequence of code words completing the modulation process is recorded onto the recording medium as it is without being subjected to the NRZI modulation processing. In the following description, this recording process without the NRZI modulation processing is referred to hereafter as a mark position recording process. In most cases, the mark edge recording process is applied to the contemporary recording medium, which has a high recording density.
In addition, a variety of modulation methods have been proposed and put to practical use. The modulation methods have been devised as methods satisfying conditions set for the recording medium as described as follows. Let Tmin and Tmax denote respectively a minimum inversion interval of a recording waveform sequence and a maximum inversion interval of the sequence. In a high-density recording process carried out in the line-velocity direction, a longer minimum inversion interval Tmin, that is, a larger minimum run d is better. In addition, in a process to reproduce blocks, it is desirable to provide a short maximum inversion interval Tmax, that is, a small maximum run k. On top of that, if an overwrite characteristic is taken into consideration, it is desirable to provide a small ratio Tmax/Tmin. In addition, from the jitter and/or S/N points of view, it is important to have a large a detection window width Tw, which is defined as the ratio m/n.
To put it concretely, the following description explains codes to be used in a process to record data onto a recording medium such as a magnetic disk, an optical disk or a magneto-optical disk by adoption of the modulation methods already proposed and/or actually put to practical use. An EFM code also referred to as a code (2, 10; 8, 17; 1) to be used in a process to record data onto a CD and/or an MD, a 8-16 code also referred to as a code (2, 10; 1, 2; 1) to be used in a process to record data onto a DVD (Digital Versatile Disc) and an RLL (Run Length Limited) (2, 7) code also referred to as a code (2, 7; m, n; r) to be used in a process to record data onto a PD having a size of 120 mm and a recording capacity of 650 MB are each an RLL code having a minimum run d of 2 (d=2). On the other hand, an RLL (1, 7) code also referred to as a code (1, 7; 2, 3; r) to be used in a process to record data onto an MO having a size of 3.5 inches and a recording capacity of 640 MB is an RLL code having a minimum run d of 1 (d=1). In addition, an RLL code having a minimum run d of 1 (d=1) and a well balanced minimum mark size as well as a well balanced conversion efficiency is a code to be often recorded onto a disk recording medium presently under research/development in a disk recording/reproduction apparatus. Examples of the disk recording medium presently under research/development are an optical disk and a magneto-optical disk that each have a high recording density.
The following table is a modulation table for the variable-length RLL (1, 7) code.
TABLE 1RLL (1, 7): (d, k; m, n; r) = (1, 7; 2, 3; 2)Data patternCode patternFor i = 11100x100100110xFor i = 20011000 00x0010000 0100001100 00x0000100 010
In the following description, the data and code patterns shown in a conversion table such as Table 1 are each referred to generically as a conversion pattern, meaning a data pattern to be converted or a code pattern obtained as a result of a process to convert the data pattern.
In the modulation table given above, symbol x is 1 if the following channel bit is 0 but symbol x is 0 if the following channel bit is 1. The maximum restrain length r is 2.
The parameters (d, k; m, n; r) of the RLL (1, 7) code are (1, 7; 2, 3; 2). The minimum inversion interval Tmin represented by an expression of (d+1)T is thus (1+1) T=2T where symbol T denotes the bit interval of the recording waveform sequence. The minimum inversion interval Tmin represented by an expression of (m/n)×2Tdata is thus (2/3)×2Tdata=1.33Tdata where symbol Tdata denotes the bit interval of the data sequence. The maximum inversion interval Tmax represented by an expression of (k+1)T is thus (7+1) T=8T. The maximum inversion interval Tmax represented by an expression of (m/n)×8Tdata is thus (2/3)×8Tdata=5.33Tdata. The detection window width Tw represented by an expression of (m/n)×Tdata is thus (2/3)×Tdata=0.67Tdata.
In a channel bit sequence completing a modulation process making use of the RLL (1, 7) code with Table 1 used as a modulation table, the generation frequency of the minimum inversion interval Tmin equal to 2T is highest to be followed sequentially by the minimum inversion intervals Tmin equal to 3T, 4T, 5T, 6T and so on. In addition, if the minimum inversion interval Tmin equal to 2T is repeated, that is, if edge information is generated much in an early period, such generation of the edge information is advantageous to generation of a clock signal in many cases.
By the way, in a process to record data onto a recording medium specially having a high recording density or reproduce data from such a recording medium, the minimum run is a parameter most likely causing an error. This is because, in a process to reproduce data from a recording medium, the output waveform having the minimum run is smaller than other output waveforms having a smaller run and is hence prone to an effect caused by an abnormal state such as a defocus or tangential-tilt state. In addition, a process to record data with consecutive minimum marks onto a recording medium having a high recording density or reproduce such data from such a recording medium is prone to an effect of an external disturbance such as a noise. Thus, a data reproduction error is generated easily. As a pattern of the data reproduction error generated in such a reproduction process, data between the front and rearmost edges of the consecutive minimum marks is mistakenly shifted all together in some cases. That is to say, the generated bit error length becomes the distance of error propagation from the head of the succession of minimum runs to the tail of the succession. Thus, there is raised a problem that the error propagation becomes undesirably long.
As control to establish a stabilized state in a process to record data onto a recording medium specially having a high line recording density or reproduce data from such a recording medium, control of minimum-run succession is effective.
As described above, before data is transmitted through a predetermined transmission line or recorded onto a recording medium, the data is modulated to convert the data into one suitable for the transmission line or the recording medium. In this case, if the code obtained as a result of the modulation process includes low-frequency components, variations and/or jitters are generated easily in a variety of error signals. The error signals represent errors such as tracking errors detected in servo control executed by a disk recording/reproduction apparatus. For this reason, it is desirable to suppress low-frequency components included in the code obtained as a result of the modulation process as much as possible.
DSV (Digital Sum Value) control is a typical method to suppress low-frequency components included in code obtained as a result of a modulation process. A DSV is a quantity obtained as follows. First of all, a channel bit sequence is subjected to a NRZI modulation process, which is a level coding process, in order to generate a bit sequence to be used as a recording code sequence. Then, each bit value of 1 in the bit sequence representing data symbols is changed to the value of +1 whereas each bit value of 0 in the bit sequence is changed to the value of −1. Subsequently, values of +1 and −1 in the resulting code are summed up to result in the DSV. The DSV is an indicator of low-frequency components included in the recording bit sequence. Thus, the DSV control is control to get rid of DC components included in the recording code sequence in order to suppress low-frequency components.
The code obtained as a result of a modulation process based on the variable-length RLL (1, 7) table given as Table 1 has not been subjected to the DSV control. In the DSV control executed on a channel bit sequence, which is a recording code sequence obtained as a result of such a modulation process, first of all, DSVs are calculated at predetermined intervals. Then, predetermined DSV control bits are inserted into the channel bit sequence used as the recording code sequence. For more information, the reader is suggested to refer to documents such as Japanese Patent Laid-open No. Hei 6-197024.
The number of DSV control bits to be inserted into the channel bit sequence is determined by the minimum run d. For a minimum run d of 1 (d=1), DSV control bits are inserted into such positions in the code word so as to abide by the minimum run d. In this case, the number of necessary DSV control bits to be inserted as channel bits is 2 (=d+1). In addition, DSV control bits are also inserted into arbitrary positions in the code word so as to abide by the maximum run k. In this case, the number of necessary DSV control bits to be inserted as channel bits is 4 (=2×(d+1)). If the DSV control is executed by inserting DSV control bits as channel bits fewer than the number of necessary DSV control bits to sustain the minimum run d and the number of necessary DSV control bits to sustain the maximum run k, there will be some cases in which the DSV control may not be executed.
In case of the RLL (1, 7) code with the parameters (d, k; m, n) set at (1, 7; 2, 3), the DSV control bits are converted into data on the basis of a conversion factor as follows:4 channel bits×2/3=8/3=2.67
Thus, the DSV control bits are converted into 2.67-bit data (or 2.67 Tdata).
By the way, the DSV control bits are basically redundant bits. Thus, from the code-conversion-efficiency point of view, it is nice to reduce the number of DSV control bits by as large a quantity as possible.
In addition, it is also nice to prevent the minimum run d and the maximum run k from being changed due to insertion of DSV control bits. This is because a change in (d, k) will undesirably have an effect on recording and reproduction characteristics.
In case of an actual RLL code, however, it is absolutely necessary to abide by the minimum run. This is because the minimum run has a big effect on recording and reproduction characteristics. Nevertheless, it is not absolutely necessary to abide by the maximum run. Thus, in some cases, there is also a format making use of a pattern violating the maximum run in a synchronization pattern. For example, the maximum run of the 8-16 code use for the DVD (Digital Versatile Disk) is 11T. However, the synchronization pattern portion is provided with a run of 14T greater than the maximum run in order to increase a capability of detecting the synchronization pattern.
Taking what is explained above into consideration, invertors of the present invention earlier proposed a 1,7PP code having parameters (d, k)=(1, 7) and Table 2 as a table of modulation adopting a modulation method tailored to even higher recording densities. For more information, the reader is suggested to refer to documents such as Japanese Patent Laid-open No. Hei 11-346154.
TABLE 21, 7PP: (d, k; m, n; r) = (1, 7; 2, 3; 4)Data patternCode pattern11*0*10001010100011010 1000010010 0000001000 100000011000 100 100000010000 100 000000001010 100 100000000010 100 000110111001 000 000 (next 010)00001000000 100 100 10000000000010 100 100 100if “xx1”, then *0* = 000“xx0”, then *0* = 101===============Sync & termination:#01 001 000 000 001 000 000 001 (24 channel bits)# = 0 indicates a sequence with no termination pattern.# = 1 indicates a sequence with a termination pattern.
<Termination table>Data patternCode pattern000000000010 100The row showing conversion patterns of “110111 001 000 000” (next 010) in the above modulation table means: When the next channel bits are “010”, the data pattern of (110111) is converted into a code pattern of “001 000 000”.
As shown in the modulation table given as Table 2, the modulation table includes data patterns to be converted into their respective code patterns. The data patterns to be converted into their respective code patterns include basic patterns, patterns to be replaced and termination patterns. The basic patterns are data patterns ranging from (11) to (000000). Without a basic pattern, the conversion process may not be carried out. The patterns to be replaced are the data patterns of (110111), (00001000) and (00000000). Even without a replacement pattern, a conversion process can be carried out. With a replacement pattern, however, an effective conversion process can be carried out. Shown on the left column of the termination table, the termination patterns of (00) and (0000) are each a pattern placed at any position in the data sequence to terminate the data sequence at the position.
In addition, the modulation table given as Table 2 for a minimum run d of 1 (d=1) and a maximum run k of 7 (k=7) includes indeterminate codes each including indeterminate bits each denoted by symbol * as bit elements of a code pattern corresponding to a basic pattern. The indeterminate bits of an indeterminate code are each determined to be a 0 or a 1 in order to abide by the minimum run d of 1 (d=1) and a maximum run k of 7 (k=7) without regard to the positions of the immediately preceding and immediately succeeding codes. To put it concretely, as is obvious from Table 2, if the 2-bit data pattern to be converted is (11), the code pattern of “*0*” selected for the 2-bit data pattern to be converted is “000” or “101”, depending on the immediately preceding code sequence (or the channel bit sequence) To be more specific, the 2-bit data pattern of (11) is converted into the code pattern of “000” or “101”, depending on the 1 bit of the immediately preceding code sequence (or the channel bit sequence). That is to say, if the 1 channel bit of the immediately preceding code sequence is “1” or the immediately preceding code sequence is “xx1”, for example, the 2-bit data pattern of (11) is converted into the code pattern of “000” in order to abide by the minimum run d. If the 1 channel bit of the immediately preceding code sequence is “0” or the immediately preceding code sequence is “xx0”, on the other hand, the 2-bit data pattern of (11) is converted into the code pattern of “101” in order to abide by the maximum run k.
The basic patterns included in the modulation table given as Table 2 have a variable-length structure. For the restrain length i set at 1 (i=1), the basic patterns are associated with 3 code patterns, i. e., “*0*”, “001” and “010”, which are fewer than the required pattern count of 4 (=2^m=2^2=4). Thus, with only the restrain length i set at 1 (i=1) in a process to convert a data sequence, there may be a data sequence that may not be converted into a code sequence. In the end, in a process convert all data sequences, it is necessary to refer to basic patterns for all restrain lengths including a restrain length i of 3 (i=3) in order for the modulation table given as Table 2 to be available as a modulation table.
In addition, the modulation table given as Table 2 also includes a replacement pattern of (110111) to be converted (or replaced) as a pattern for controlling the succession of minimum runs d. The replacement data pattern of (110111) is converted into a code pattern as follows. If the data pattern is (110111), the following code word sequence is referred to. If the following code word sequence is “010”, the 6-bit data pattern of (110111) is converted into a code pattern of “001 000 000”. If the following code word sequence is not “010”, on the other hand, the data pattern of (110111) is replaced with a data pattern of ((11, (01), (11)) having 2-bit data units. Eventually, the data pattern of ((11, (01), (11)) is converted into a code word of “*0* 010 *0*”. Thus, in the code word sequence obtained as a result of converting the data, the succession of minimum runs d is restricted. That is to say, the minimum run can be repeated up to six times at the most.
In the modulation table given as Table 2, the maximum restrain length r is 4 (r=4). Patterns provided with a restrain length i set at 4 (i=4) as patterns to be converted include the patterns to be replaced as patterns for realizing a maximum run k of 7 (k=7). The patterns for realizing a maximum run k of 7 (k=7) are each referred to hereafter as a maximum-run assuring pattern. The patterns for realizing a maximum run k of 7 (k=7) are a data pattern of (00001000) and a data pattern of (00000000). The data pattern of (00001000) is converted into a code pattern of “000 100 100 100” whereas the data pattern of (00000000) is converted into a code pattern of “010 100 100 100”. Also in this case, the minimum run d of 1 (d=1) is obeyed.
In addition, the modulation table given as Table 2 also includes data patterns of (00) and (0000) to be located at any termination positions in a data sequence as termination patterns immediately preceding a synchronization pattern. A termination pattern located at any termination position in a data sequence is used to terminate the data sequence at the position. The 1-bit code word at the head of an inserted synchronization pattern is a bit indicating whether or not a termination pattern has been used. That is to say, if a termination pattern has been used, the 1-bit code word at the head of an inserted synchronization pattern sequence immediately following the termination pattern is set at “1”. If no termination pattern has been used, on the other hand, the 1-bit code word at the head of an inserted synchronization pattern sequence immediately following the termination pattern is set at “0”. It is to be noted that the synchronization pattern in the modulation table given as Table 2 includes the 1-bit code word located at the head of the synchronization pattern sequence as a bit indicating whether or not a termination pattern has been used at a location immediately preceding the synchronization pattern and a code pattern repeated twice to create a synchronization detection pattern as a code pattern for a maximum run k set at 8 (k=8) greater than the maximum run k of 7 (k=7). Thus, the synchronization pattern is a code word having a total of 24 channel bits.
By the way, the modulation table given as Table 2 establishes a conversion rule for conversion patterns each provided on a row as a pattern pair consisting of a data pattern and a code pattern. In accordance with the conversion rule, a remainder obtained as a result of an operation to divide the number of 1s included as bit elements in a data pattern serving as a pattern to be converted into a code pattern by 2 and a remainder obtained as a result of an operation to divide the number of 1s included as bit elements in the code pattern resulting from the conversion process by 2 are both 1 or 0. The remainder of 1 indicates that both the number of 1s included in the data pattern and the number of 1s included in the data pattern are odd. On the other hand, the remainder of 0 indicates that both the number of 1s included in the data pattern and the number of 1s included in the data pattern are even. For example, a data pattern of (000001) corresponds to a code pattern of “010 100 100”. In this case, the number of 1s included as bit elements in the data pattern is 1 while the number of 1s included as bit elements in the code pattern is three. If the number of 1s included as bit elements in the data pattern and the number of 1s included as bit elements in the code pattern are divided by 2, the remainders obtained as a result of the division operations agree with each other, being both equal to 1 indicating that both the number of 1s included in the data pattern and the number of 1s included in the code pattern are odd. As another example, a data pattern of (000000) corresponds to a code pattern of “010 100 000”. In this case, the number of 1s included as bit elements in the data pattern is 0 while the number of 1s included as bit elements in the code pattern is 2. If the number of 1s included as bit elements in the data pattern and the number of 1s included as bit elements in the code pattern are divided by 2, the remainders obtained as a result of the division operations agree with each other, being both equal to both 0 indicating that both the number of 1s included in the data pattern and the number of 1s included in the code pattern are even.
As described above, the modulation table given as Table 2 includes only conversion patterns forming pattern pairs each consisting of a data pattern and a code pattern wherein a remainder obtained as a result of an operation to divide the number of 1s included in the data pattern agrees with a remainder obtained as a result of an operation to divide the number of 1s included in the code pattern are both 0 or 1, indicating that the number of is included in the data pattern and the number of 1s included in the code pattern are both even or odd. Such a pair of data and code patterns is referred to as a pair of even/odd-characteristic retaining conversion patterns. That is to say, the modulation table given as Table 2 does not include conversion patterns forming pattern pairs each consisting of a data pattern and a code pattern wherein a remainder obtained as a result of an operation to divide the number of 1s included in the data pattern does not agree with a remainder obtained as a result of an operation to divide the number of 1s included in the code pattern. Such a pair of data and code patterns is referred to as a pair of even/odd-characteristic retention violating conversion patterns.
Next, a method of executing the DSV control is described. DSV control is not executed for conversion patterns of a modulation table such as Table 1 for the RLL (1, 7) code. In this case, the existing DSV control is executed typically by modulating the data sequence and then adding at least (d+1) DSV control bits at predetermined intervals to a channel bit sequence obtained as a result of the modulation process. Much like the existing DSV control, DSV control can be executed for conversion patterns of the modulation table given as Table 2. However, the DSV control can be executed with an even higher degree of efficiency by making use of relations between the data patterns and the code patterns. That is to say, with Table 2 establishing a conversion rule in accordance with which a remainder obtained as a result of an operation to divide the number of 1s included as bit elements in a data pattern serving as a pattern to be converted into a code pattern by 2 and a remainder obtained as a result of an operation to divide the number of 1s included as bit elements in the code pattern resulting from the conversion process by 2 are both 1 or 0, an operation to insert a DSV control bit of 1 indicating inversion or 0 indicating non-inversion into the channel bit sequence as described earlier is equivalent to an operation to insert respectively a DSV control bit of 1 for inversion or 0 for non-inversion into the data bit sequence.
For example, in the modulation table given as Table 2, 3 data bits to be converted are (001) immediately preceding a DSV control bit behind the data bits. In this case, the data can be represented by a pattern of (001-x), where symbol x denotes 1 bit having the value of 0 or 1. For x=0, the data pattern is (0010) and included in the modulation table given as Table 2 as follows.
Data patternCode pattern0010010 000In this case, the data pattern of (0010) is converted into a code pattern of “010 000”.
For x=1, on the other hand, the data pattern is (0010) and included in the modulation table given as Table 2 as follows.
Data patternCode pattern0011010 100In this case, the data pattern of (0011) is converted into a code pattern of “010 100”. Then, a code patterns obtained as a result of conversion is subjected to an NZRI modulation process in order to generate a level code sequence as follows:
Data patternCode patternLevel code sequence0010010 0000111110011010 100011000
The last 3 bits in one of the level code sequences are obtained by inversion of the last 3 bits in the other level code sequences. The result implies that by selecting the DSV control bit 0 or 1, the DSV control can be executed inside the data sequences.
If redundancy of the DSV control is taken into consideration, execution of the DSV control by making use of 1 bit in a data sequence corresponds to execution of DSV control by making use of 1.5 bits added to the channel bit sequence due to the fact that the conversion factor m/n of the modulation table given as Table 2 is 2/3 (that is, m:n=2:3). In order to execute DSV control for the RLL (1, 7) code modulation table like the one shown as Table 1, on the other hand, it is necessary to execute the DSV control for the channel bit sequence. Thus, in comparison with the DSV control for the modulation table given as Table 2, the degree of redundancy undesirably increases. In other words, by executing DSV control within the data sequence in the structure of the modulation table given as Table 2, the DSV control can be executed with a high degree of efficiency.
The modulation table given as Table 2 for a code provided with a minimum run r of 1 and a maximum run d of 7 ((d, k)=1, 7)) as a code to be recorded onto a recording medium having a high recording density is used as a table for creating a recording format in, among others, Blu-ray Disc ReWritable ver 1.0 (a trademark of a high-density optical disk system).
A more stable system is expected as a system that can be implemented by also adoption of a modulation method for future higher-density recording. To put it concretely, such a more stable modulation system is expected for, among others, higher-density specifications set for high-density optical disks.
In this case, if it is possible to realize a modulation method for implementing a more stable system as a modulation system realizable by making use of the configuration of a similar modulation table for a code having the same parameters as those of the existing (1, 7) PP code for Blu-ray Disc ReWritable ver 1.0, which has already been made available in the market as a commercial product, the existing design technology can be applied. Thus, it is possible to reduce the number of design risks encountered in the process to design hardware for realizing the modulation system.